The present invention relates in general to voltage translators, and more particularly, to an ECL to TTL/CMOS logic level translator operative with a single power supply and utilizing time constants for controlling the slew rate of the propagating signal to prevent current spikes in the output switching stage.
It is well known that many of today's complex systems mix and match integrated circuits (ICs) of different logic families to accomplish a series of interrelated functions. In one example, signals produced in one logic family, ECL, are translated to levels compatible with another logic family, TTL, or possibly CMOS, for further processing. A typical ECL to TTL/CMOS translator converts a differential ECL input signal to first and second complementary control voltages for driving upper and lower transistors of an output stage, respectively. The collector-emitter conduction paths of the upper and lower transistors are serially coupled between a positive supply voltage, V.sub.CC, and ground potential, and the complementary control voltages are generated in separate conduction paths coupled between power supplies, V.sub.CC and V.sub.EE, typically operating at 5 volts and -5 volts, respectively. During logic transitions, however, as the differential ECL input signal passes through zero, the upper and lower transistors of the output stage may conduct simultaneously allowing undesirably large currents to flow therebetween. These current spikes induce noise into the power supplies causing a myriad of problems in adjacent circuits including false logic switching. As the frequency of operation increases so does the magnitude of the current spikes and, correspondingly, the extent of the noise problem.
Another limitation of the conventional ECL to TTL/CMOS translator is the requirement for dual power supplies. It would be desirable for the translator to be operative with a single power supply simplifying the interface to external circuitry wherein a dual power supply is not readily available.
Hence, there is a need for an improved ECL to TTL/CMOS translator which eliminates current spikes in the output stage during logic transitions and operates with a single power supply.